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INTEGRATED CIRCUITS
DATA SHEET
74AHC373; 74AHCT373 Octal D-type transparent latch; 3-state
Product specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC06 1999 Nov 23
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V * Balanced propagation delays * All inputs have Schmitt-trigger actions * Inputs accepts voltages higher than VCC * Common 3-state output enable input * Functionally identical to the `533', `563' and `573' * For AHC only: operates with CMOS input levels * For AHCT only: operates with TTL input levels * Specified from -40 to +85 C and -40 to +125 C. DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 C; tr = tf 3.0 ns.
74AHC373; 74AHCT373
The 74AHC/AHCT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The `373' consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The `373' is functionally identical to the `533', `563' and `573', but the `533' and `563' have inverted outputs and the `563' and `573' have a different pin arrangement.
TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay Dn to Qn; LE to Qn input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND 4.3 3.0 4.0 10 4.3 3.0 4.0 12 AHCT ns pF pF pF UNIT
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODES OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; L L L L H H LE H H L L X X Dn L H I h X X
74AHC373; 74AHCT373
INTERNAL LATCHES L H L H X X
OUTPUTS Q0 to Q7 L H L H Z Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don't care; Z = high-impedance OFF-state. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC373D 74AHC373PW 74AHCT373D 74AHCT373PW PINNING PIN 1 2, 5, 6, 9, 12, 15, 16 and 19 3, 4, 7, 8, 13, 14, 17 and 18 10 11 20 OE Q0 to Q7 D0 to D7 GND LE VCC SYMBOL latch outputs data inputs ground (0 V) latch enable input (active HIGH) DC supply voltage DESCRIPTION output enable input (active LOW) PACKAGES NORTH AMERICA PINS 74AHC373D 74AHC373PW DH 74AHCT373D 7AHCT373PW DH 20 20 20 20 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT163-1 SOT360-1 SOT163-1 SOT360-1
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
OE 1 Q0 2 D0 3 D1 4 Q1 5
20 VCC 19 Q7 18 D7 17 D6 16 Q6
handbook, halfpage
11 3 4 7 8 13 14 17 18 LE D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
373
Q2 6 D2 7 D3 8 Q3 9 GND 10
MNA185
15 Q5 14 D5 13 D4 12 Q4 11 LE
MNA186
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1 11
EN C1 2 5 6 9 12 15 16 19
MNA187
3 4 7 8 13 14 17 18
1D
Fig.3 IEC logic symbol.
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS
Q0 Q1 Q2 Q3
2 5 6 9
handbook, halfpage
LE
Q4 12 Q5 15 Q6 16 Q7 19 D Q LE
MNA189
LE LE
11 LE 1 OE
MNA184
Fig.4 Functional diagram.
Fig.5 Logic diagram (one latch).
D0
D1
D2
D3
D4
D5
D6
D7
handbook, full pagewidth
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA199
Fig.6 Logic diagram.
1999 Nov 23
5
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
RECOMMENDED OPERATING CONDITIONS
74AHC373; 74AHCT373
74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature see DC and AC characteristics per device VCC = 3.3 0.3 V VCC = 5 0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 - - TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40
74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V C
+125 -40 100 20 - -
+125 C - 20 ns/V ns/V
tr,tf (t/f) input rise and fall rates
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO package: above 70 C the value of PD derates linearly with 8 mW/K. For TSSOP package: above 60 C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage DC input diode current DC output diode current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +125 C; note 2 VI < -0.5 V; note 1 VO < -0.5 V or VO > VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 20 25 75 500 V V mA mA mA mA mW
DC output source or sink current -0.5 V < VO < VCC + 0.5 V
+150 C
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
DC CHARACTERISTICS
74AHC373; 74AHCT373
Family 74AHC Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 4.0 mA VI = VIH or VIL; IO = 8.0 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (C) -40 to +85 - - 0.5 0.9 1.65 - - - -40 to +125 UNIT - - 0.5 0.9 1.65 - - -
MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V V V V V V V V V V V V V V V V A
3.85 -
3.85 -
3.85 -
2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3
2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 2.5 40 10
2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0
VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 -
0.25 - 4.0 10 - -
10.0 A 80 10 A pF
1999 Nov 23
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
Family 74AHCT Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 8.0 mA II IOZ input leakage current 3-state output OFF current VI = VIH or VIL VCC (V) - - 4.5 25 - 0.8 - - 0.1 0.36 0.1 Tamb (C) -40 to +85 - 0.8 - - 0.1 0.44 1.0 2.5 -40 to +125 UNIT - 0.8 -
MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - 4.4 3.8 - - - 2.0 - 4.4 V V V V V V A
4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.5 4.5 4.5 5.5 4.4
3.94 - - - - - 0 - - -
3.70 - - - - - 0.1 0.55 2.0
VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0
0.25 -
10.0 A
ICC ICC
quiescent supply current additional quiescent supply current per input pin input capacitance
-
- -
4.0 1.35
- -
40 1.5
- -
80 1.5
A mA
4.5 to 5.5 -
CI
-
-
3
10
-
10
-
10
pF
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
AC CHARACTERISTICS 74AHC373 Ground = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL tPHZ/tPLZ tPHL/tPLH propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay OE to Qn propagation delay OE to Qn clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP see Figs 8 and 11 see Figs 10 and 11 see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 15 pF - - - - 50 pF - - - - 5.0 4.0 1.0 6.0 6.3 5.6 5.6 7.8 8.3 7.5 9.2 - - - CL MIN. 25 TYP.
74AHC373; 74AHCT373
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
11.4 11.0 11.4 10.0 14.9 14.5 14.9 13.3 - - -
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 1.0
13.5 13.0 13.5 12.0 17.0 16.5 17.0 15.0 - - -
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 1.0
14.5 14.0 14.5 13.0 19.0 18.5 19.0 17.0 - - -
ns ns ns ns ns ns ns ns ns ns ns
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL tPHZ/tPLZ tPHL/tPLH propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL tPHZ/tPLZ tW tsu th Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. propagation delay OE to Qn propagation delay OE to Qn clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP see Figs 8 and 11 see Figs 10 and 11 see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 15 pF - - - - 50 pF - - - - 5.0 4.0 1.0 4.0 4.3 3.8 4.3 5.3 5.6 5.2 6.4 - - - 7.2 7.2 8.1 7.2 9.2 9.7 10.1 9.2 - - - CL MIN. 25 TYP.
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 1.0
8.5 8.5 9.5 8.5 10.5 11.1 11.5 10.5 - - -
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 1.0
9.0 9.0 10.5 9.5 11.5 12.5 13.0 11.5 - - -
ns ns ns ns ns ns ns ns ns ns ns
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHCT373 Ground = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay see Figs 7 and 11 Dn to Qn propagation delay see Figs 8 and 11 LE to Qn tPZH/tPZL tPHZ/tPLZ tPHL/tPLH propagation delay see Figs 9 and 11 OE to Qn propagation delay OE to Qn propagation delay see Figs 7 and 11 Dn to Qn propagation delay see Figs 8 and 11 LE to Qn tPZH/tPZL tPHZ/tPLZ tW tsu th Note 1. Typical values at VCC = 5.0 V. propagation delay see Figs 9 and 11 OE to Qn propagation delay OE to Qn clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP see Figs 8 and 11 see Figs 10 and 11 15 pF - - - - 50 pF - - - - 6.5 3.5 1.5 4.0 4.3 4.0 4.4 5.2 5.5 5.2 6.5 - - - 8.5 CL MIN. 25 TYP.
74AHC373; 74AHCT373
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.5 3.5 1.5
9.5 13.5 12.5 11.0 10.5 14.5 13.5 12.0 - - -
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.5 3.5 1.5
11.0 15.5 14.0 13.0 12.0 17.0 15.0 14.0 - - -
ns ns ns ns ns ns ns ns ns ns ns
12.3 10.9 10.2 9.5 13.3 11.9 11.2 - - -
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
AC WAVEFORMS
74AHC373; 74AHCT373
handbook, halfpage
Dn input
VM
tPHL
tPLH
Qn output
VM
tTHL
tTLH
MNA190
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
Fig.7 The input (Dn) to output (Qn) propagation delays and the output transition times.
handbook, full pagewidth
LE input
VM tW tPHL
tPLH
Qn output
VM
tTHL
tTLH
MNA191
FAMILY AHC AHCT Fig.8
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
The Latch Enable (LE) input pulse width, the latch enable input to output (Qn) propagation delays and the output transition times.
1999 Nov 23
12
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, full pagewidth
VI OE input GND tPLZ output LOW-to-OFF OFF-to-LOW VCC VM VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
MNA450
VM(1)
tPZL
VOL + 0.3 V tPZH VOH - 0.3 V VM
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
Fig.9 The 3-state enable and disable times.
handbook, full pagewidth
Dn input
VM
th tsu tsu
th
LE input
VM
MNA193
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.10 The data set-up and hold times for Dn input to LE input.
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA183
VO
1000
VCC open GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH VCC
S1 open GND
Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter "AC characteristics"). RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.11 Test circuitry for switching times.
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm
74AHC373; 74AHCT373
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1999 Nov 23
15
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153AC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-06-16 95-02-04
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74AHC373; 74AHCT373
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Nov 23
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable REFLOW(1)
1999 Nov 23
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
NOTES
74AHC373; 74AHCT373
1999 Nov 23
19
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/02/pp20
Date of release: 1999
Nov 23
Document order number:
9397 750 06298

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